Effects of Different Clock Gating Techinques on Design
نویسنده
چکیده
Low power is one of the most important issues in today’s ASIC (Application Specific Intregated Circuit) design. As the transistor is scaled down, power density becomes high and there is urgent need of reduction in power. The clock gating is one of the most elegant and classic techniques for reduction of power. Clock gating can be implemented by using any of these three cells, (1) Latch based cell (2) Flip-Flop based cell (3) Gate based cell. In this paper, we demonstrate the effect of different Clock Gating cells in design and how the design metrics, area, power and performance are affected for each clock gating cell. There are two variations in each clock gating cell, one is with Reset and other is without Reset. In this paper we also demonstrate how the design metric is affected by insertion of Reset signal in each Clock Gating cell.
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